It is known to provide a data processing apparatus having logic elements which can communicate with each other over a communication channel. Communication between the logic elements occurs via transfers which may be issued from one logic element (referred to herein as the initiator logic element or initiator circuitry) to another logic element (referred to herein as the recipient logic element or recipient circuitry) via the communication channel. Often, the data processing apparatus will include multiple logic elements, and individual logic elements may be able to act as initiator logic elements for certain transfers and recipient logic elements for other transfers. Each transfer will typically consist of some payload data and associated control data and the communication channel over which the transfer takes place will typically consist of one or more communication paths between the initiator circuitry and the recipient circuitry. Whilst it is often the case that the payload data and the associated control data follow the same path between the initiator circuitry and the recipient circuitry, it is possible that quite distinct paths may be provided for the payload data and the associated control data, with those distinct paths forming the communication channel.
In a data processing apparatus having multiple logic elements, it is known to provide bus logic for providing the required communication paths used to form the communication channels between the various logic elements. One example of such bus logic is an interconnect circuit which provides multiple connections over which communication paths can be established between initiator logic elements and recipient logic elements.
Typically a clock signal is used to control the operation of various logic elements within the data processing apparatus, and to control the transfer of signals between those logic elements. When designing such an apparatus, regard will usually be taken of the target clock speed, i.e. operating frequency, that the apparatus will need to run at, since this will ultimately limit how much processing a particular logic element can perform in a single clock cycle, and how far a signal may pass along a communication path in each clock cycle.
As data processing apparatus increase in complexity, so the interconnect circuitry or the like used to provide the various communication paths between the logic elements of the data processing apparatus also increases in complexity, and such interconnect circuitry may provide paths therein that could fail to meet the timing requirements set by the target clock speed for the system. One known technique to seek to reduce the likelihood of certain paths failing timing requirements involves the use of a register slice component added into a particular communication path in order to separate that path into distinct path portions, with the payload data and associated control data being temporarily stored in the register slice prior to being propagated along the next path portion. Hence, the register slice component alleviates the timing problem by dividing a particular path into two parts, at the cost of adding a clock cycle of latency and a large number of flops. More details of such register slice components are described for example in commonly assigned U.S. Pat. No. 7,069,376, the entire contents of which are hereby incorporated by reference.
As discussed earlier, interconnect circuitry will typically provide a plurality of connections over which communication paths can be established coupling multiple logic elements, and the way in which the various transfers are routed via those communication paths will be dependent on the bus protocol employed within the interconnect circuitry. One known type of bus protocol that has been developed is known as the split transaction protocol. In accordance with such a split transaction protocol, the plurality of communication paths within the interconnect circuitry provide at least one address channel for carrying address transfers and at least one data channel for carrying data transfers. An example of such a split transaction protocol is the AXI (Advanced eXtensible Interface) protocol developed by ARM Limited, Cambridge, United Kingdom. The AXI protocol provides a number of channels over which payload data and associated control data can be transferred, these channels comprising a read address channel for carrying address transfers of read transactions, a write address channel for carrying address transfers of write transactions, a write data channel for carrying data transfers of write transactions, a read data channel for carrying data transfers of read transactions, and a write response channel for returning transaction status information to a master logic element at the end of a write transaction, such transaction status information indicating for example whether the transaction completed successfully, or whether an error occurred, etc.
Whilst the above-mentioned register slice components can be used in a variety of different embodiments in order to alleviate timing constraints in communication paths, one particular embodiment where they are used is in interconnect circuits conforming to the AXI protocol. Currently there are three different variants of register slice component which can be used in such interconnect circuits, all of which require one or more arrays of flops to satisfy their functional and behavioural requirements.
Table 1 below shows the number of flops required for each register slice type and data width in association with the data path, i.e. to register the payload data, and does not include any additional flops used as part of the control mechanism:
TABLE 1Type32-bit64-bit128-bitFully registered388524796Forward path194262398Reverse path194262398
It should be noted that the figures in Table 1 above are based on the signal set provided in the AMBA AXI protocol specification, and do not include any additional signals that may have been added or extended since that release. However, it is clear from the above figures that a large number of flops are required for each register slice component inserted within a communication path of the interconnect circuitry. Although silicon real estate is reasonably cheap in modern technologies, there are cases where the current register slice components may be considered too large, for example in FPGA or tightly constrained modular designs.
Accordingly, it would be desirable to provide a simpler mechanism for alleviating timing constraints for payload data passing over a communication channel within a data processing apparatus.